Gate driving apparatus
US8760200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2013 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Apr 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate driving apparatus according to the embodiment includes a first switching device, a second switching device that outputs a signal to charge a capacitance of the first switching device, a third switching device connected in parallel to the second switching device to prevent a drop of a voltage output from the second switching device, and a fourth switching device that outputs a signal to discharge the capacitance of the first switching device. An NMOS transistor is used as a main switching device and a PMOS transistor connected in parallel to the NMOS transistor is used as a sub-switching device, so that the chip size is reduced without dropping the output voltage of the gate driving apparatus. The loss of the switching device is prevented by preventing the output voltage of the gate driving apparatus from being dropped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.