Content addressable memory
US8760900B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 19, 2013 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Feb 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.