Multiple bitcells tracking scheme semiconductor memory array
US8760948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Dec 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read tracking system and method for advanced memory devices are provided. The read tracking system and method include tracking multiple tracking bit cells in multiple segments and columns to incorporate device performance variation of bit cells in the memory array. The tracking path mimics the worst-case read path with some built-in margins to sufficiently and efficiently cover the read times of bit cells in a memory array without unnecessarily sacrificing the read speed performance of the memory array. A number of tracking cells may be placed at different segments and both sides of the memory array to cover read time variation across memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.