Overlapping interconnect signal lines for reducing capacitive coupling effects
US8760952B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2010 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Oct 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.