Digital receivers
US8761325B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jun 28, 2010 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Dec 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock generator generates a clock signal used for sampling a received signal by a comparator which compares the received signal to a reference. A phase shifter adjusts the phase of the first clock signal and a controller adjusts the phase of the clock signal to maximize the vertical eye opening of the signal at the sampling time. In an example embodiment, the phase of the clock signal is adjusted in a first direction and a measure of vertical eye opening of the signal is compared to a previous measure. If the measure of vertical eye opening has increased the signal another phase adjustment is made in the same direction and if the vertical eye opening of the signal has decreased a further phase adjustment in the opposite direction is made. By increasing the vertical eye opening of the signal the signal-to-noise ratio of the received signal is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.