Rational clock divider for media timestamps and clock recovery functions
US8761327B2 · kind B2 · utility
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3References
20Claims
0Family size
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Key dates
| Filing date | Jun 14, 2011 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Mar 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal, and using the second clock signal to drive software timer logic and generate media timestamps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.