Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment
US8762127B2 · kind B2 · utility
12Cited by
18References
19Claims
0Family size
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Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Mar 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.