Direct memory access controller with multiple transaction functionality
US8762596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2011 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | May 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.