Digital delay buffers and related methods
US8762600B2 · kind B2 · utility
0Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2004 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Aug 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0623
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital delay buffer may be provided with both a fast processing, small capacity memory section and a slow processing, large capacity memory section. The use of two memory sections allows the buffer to generate an aligned data stream with n-bit block level latencies from a plurality of delayed data portions, even if one of the portions is subjected to an undue delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.