Memory access consolidation for SIMD processing elements using transaction identifiers
US8762691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Mar 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.