Method and apparatus for detecting memory access faults
US8762797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Nov 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Detecting a fault in the operation of a computer having a processor and a memory is taught. Instrumentation code is placed within an application program during compilation, and runtime library routines are modified to support detection of invalid memory accesses. Memory space is divided into application, shadow and unmapped memories. When accessing application memory at an original address, an address in shadow memory is computed by shifting the address and adding an offset. If the value stored at the shadow address indicates that the original address is invalid (e.g., not allocated or already freed), then error reporting code is executed that indicates the type of error and the location and optionally halts the computer. Invalid memory references to heap, stack and global objects in application memory can be detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.