Error prediction in logic and memory devices
US8762804B2 · kind B2 · utility
4Cited by
4References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 6, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Aug 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.