System and methods for performing decoding error detection in a storage device
US8762818B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2010 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Feb 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
System and methods for performing decoding error detection in a storage device are provided. Data bits of a data polynomial may be retrieved from a storage device. The data bits may be arranged in a first order. Error correction may be performed on the retrieved data bits of the data polynomial to produce an error polynomial based on error correction parity information encoded in the data polynomial. Bits of the error polynomial are arranged in a second order that is reverse to the first order. A first remainder of the error polynomial may be computed based on data bits corresponding to the data polynomial arranged in the second order. An error in the error polynomial may be detected based on the computed first remainder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.