System and method for automatic timing-based register placement and register location adjustment in an integrated circuit (IC)
US8762909B1 · kind B1 · utility
1Cited by
6References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a method for register placement in an integrated circuit (IC) includes determining a data path between circuit elements, placing at least one register along the data path, performing a static timing analysis on the data path, extracting top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments; processing the top-level timing data to determine whether the extended timing path violates a timing requirement, and moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.