System and method for integrated circuit die size reduction
US8762915B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2010 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Jun 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit analysis tool is provided for die size reduction analysis. A processor determines a first initial output slack time. If the first initial output slack time is greater than zero, a first circuit element is modeled with a second die area, less than the first die area. The second die area is associated with a third delay greater than the first delay. Then, the second data signal is modeled equal to the first data signal with the third delay. If a first modified output slack time is greater than or equal to zero, the first circuit element first die can be replaced with the second die. If the first modified output slack time is a first value less than zero, a first delay is added to the clock signal that is greater than or equal to the first value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.