Implementing linearly weighted thermal coded I/O driver output stage calibration
US8766663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2012 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Dec 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.