Overvoltage protection circuit
US8766675B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit includes: a pull down circuit including a first PFET and a second PFET connected in series between a pad of a USB circuit and ground; and a pull up circuit including a first NFET and a second NFET connected in series between the pad and a supply voltage. The circuit includes: a third PFET connected to a gate of the first PFET and a gate of the second PFET; a third NFET connected to a gate of the first NFET and a gate of the second NFET; a fourth PFET connected to the first NFET and the second NFET; and a fourth NFET connected to the first PFET and the second PFET. A pad voltage has a nominal minimum and maximum. Each of the first PFET, the second PFET, the first NFET, and the second NFET has a nominal voltage less than the pad voltage nominal maximum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.