Phase locked loop circuit and a method in the phase locked loop circuit

US8766685B1 · kind B1 · utility

Assignee

• Beken Corporation · CN

Inventors

• Yunfeng Zhao · Shanghai, CN
• Ronghui Kong · Shanghai, CN
• Dawei Guo · Shanghai, CN

Key dates

• Filing date: Jun 6, 2013
• Grant date: Jul 1, 2014
• Expiry date: Jun 6, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/104
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A PLL circuit comprises a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), a frequency divider (FD) and a reset module. The PFD receives a first and a second input signals, and outputs a first and a second adjustment parameters according to phase and frequency difference between the first and the second input signal. The CP is coupled to the PFD, generates a current according to the first and the second adjustment parameters. The LPF is coupled to the CP, and generates a voltage according to the current. The VCO is coupled to the LPF, and generates an oscillation frequency according to the voltage. The FD receives and divides the oscillation frequency, and generates the second input signal. The reset module generates a reset signal to feed to the FD, wherein the reset module receives the first signal.