Integrated circuit
US8766710B1 · kind B1 · utility
1Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2012 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Aug 21, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising: a first core circuit configured to operate at a first clock rate for carrying out a first range of tasks; and a second core circuit configured to operate in a first mode and a second mode, the second core circuit being configured to operate at a second clock rate for carrying out a second range of tasks in the second mode and being configured to operate in the second mode when the first core circuit carries out the first range of tasks, the second clock rate being greater than the first clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.