Methods and devices for folded push pull power amplifiers
US8766723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2012 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Jun 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and devices provide for power amplification in a push pull power amplifier. A circuit comprises an input stage, a power amplifier stage and an output stage. The input stage provides a plurality of control voltages based on a control current. The input stage may include a transformer with a primary side and two secondary sides. A power amplifier stage comprises an NMOS transistor and a PMOS transistor arranged in a push-pull configuration to generate a plurality of amplified signals. The transistors may be in a common gate arrangement. The output stage combines the amplified signals and generates an output voltage. The output stage may include a transformer with two primary sides and a secondary side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.