Parallel apparatus for high-speed, highly compressed LZ77 tokenization and Huffman encoding for deflate compression
US8766827B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2013 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Mar 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3084
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Parallel compression is performed on an input data stream by processing circuitry. The processing circuitry includes hashing circuitry, match engines, pipeline circuitry and a match selector. The hashing circuitry identifies multiple locations in one or more history buffers for searching for a target data in the input data stream. The match engines perform multiple searches in parallel for the target data in the one or more history buffers. The pipeline circuitry performs pipelined searches for multiple sequential target data in the input data stream in consecutive clock cycles. Then the match selector selects a result from the multiple searches and pipelined searches to compress the input data stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.