Synchronization system for a wireless receiver
US8767892B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2013 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Jun 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0095
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A synchronization system for initial setup of phases of local oscillators in a wireless receiver of a communication system characterized by transmission of data packets having a predetermined preamble consisting of M identical sections of L symbols followed by a single section of the same kind, multiplied by −1, and wherein the wireless receiver is operative to perform decimation in an RF demodulator. The synchronization system includes a twofold correlator, an accumulator, a multipler, a threshold comparator, a carrier phase former and a clock phase former, and operates at a decimated symbols frequency, and performs not only preamble detection, but also symbols clock phase detection together with carrier phase detection, while enabling the theoretically possible noise immunity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.