Speech recognition circuit using parallel processors
US8768696B2 · kind B2 · utility
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7References
2Claims
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Key dates
| Filing date | Oct 5, 2011 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Jul 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L15/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A speech recognition circuit comprises a memory containing lexical data for word recognition, the lexical data comprising a plurality of lexical data structures stored in each of a plurality of parts of the memory; and a parallel processor structure connected to the memory to process speech parameters by performing parallel processing on a plurality of the lexical data structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.