Saving and restoring states through low power mode
US8769338B1 · kind B1 · utility
1Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2010 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Nov 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is disclosed including one or more communication devices, an operational controller configured by a state device in a normal mode for the communication device, which may consume more power than in a low power mode. The operational controller retains an operational state in a normal mode for the communication device that may be corrupted during low power mode. A save-restore processor operates a configuration bus and an essentially non-volatile memory at the start a low power mode to retain the operational state and end of the low power mode to restore the operational state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.