Performing a cyclic redundancy checksum operation responsive to a user-level instruction
US8769386B2 · kind B2 · utility
3Cited by
46References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2013 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/157
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.