Timing closure in chip design
US8769470B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2011 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a method and system for improving timing closure in chip design. The method comprises: identifying a critical timing path in a chip design pattern, wherein a timing window of the critical timing path is smaller than a predetermined timing window; determining a variation of each segment of the critical timing path, wherein the variation indicates uncertainty of delay of a device and/or a wire caused by one or more factors; and changing at least one segment of the critical timing path based on the variation of each segment of the critical timing path to enlarge the timing window of the critical timing path. The method and system may enlarge a timing window of a critical timing path by reducing the variation thereof, thereby achieving timing closure in the chip design pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.