Patent · US Active

Latency hiding of traces using block coloring

US8769513B2 · kind B2 · utility

0Cited by

15References

28Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Xiaofeng Guo · Shanghai, CN
Jinquan Dai · Shanghai, CN
Long Li · Shanghai, CN
Zhiyuan Lv · Shanghai, CN

Key dates

Filing date	Nov 18, 2005
Grant date	Jul 1, 2014
Priority date	—
Expiry date	Jul 8, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3851
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information. The blocks correspond to a program trace and containing a wait instruction. The wait instruction is sunk down the blocks globally to the end of the critical section using the color information and a dependence constraint on the wait instruction.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.