Image sensor arrangement
US8772695B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2011 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | May 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Each column of pixels in an image sensor array has at least two column bitlines connected to an output of each pixel. A readout input circuit includes first inputs and a second input. Each first input is connected, via a capacitance, to a comparator input node. The second input is connected via a capacitance to the same comparator input node. The first inputs receive, in parallel, an analog signal acquired from the pixels via the column bitlines. The analog signals vary during a pixel readout period and have a first level during a first calibration period and a second level during a second read period with the analog signals being constantly read onto the capacitances during both the first calibration period and the second read period. The comparator compares an average of the signals on the plurality of first inputs to the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.