Systems, devices, and methods for analog processing
US8772759B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2012 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Oct 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/805
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.