Semiconductor wafer including lattice matched or pseudo-lattice matched buffer and GE layers, and electronic device
US8772830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2008 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Jul 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be formed then annealing with a temperature and duration that enables movement of crystal defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.