Mask programmable interface selection
US8772915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a semiconductor die with on-die preferred interface selection includes at least two groups of pads situated on an active surface of the semiconductor die, where each of the at least two groups of pads is coupled to its associated interface in the die. A set of bumps is mask-programmably routed to one of the at least two groups of pads, thereby selecting the preferred interface for the semiconductor die. A non-preferred interface is not routed to any bumps on the active surface of the semiconductor die, thereby reducing bump count on the die. Each of the at least two groups of pads can be situated in a corresponding pad ring on the active surface of said semiconductor die. The at least two groups of pads can be laid out substantially inline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.