Increased surface area electrical contacts for microelectronic packages
US8772930B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2012 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Jan 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer microelectronic device package includes one or more vertical electrical contacts. At least one semiconductor material layer is provided having one or more electrical devices fabricated therein. An electrical contact pad can be formed on or in the semiconductor material layer. Another material layer is positioned adjacent to the semiconductor material layer and includes a conductive material stud embedded in or bonded to the layer. A via is formed through at least a portion of the semiconductor material layer and the electrical contact pad and into the adjacent layer conducting material stud. The via is constructed such that the via tip terminates within the conducting material stud, exposing the conducting material. A metallization layer is disposed in the via such that the metallization layer contacts both the electrical contact pad and the conducting material stud exposed by the via tip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.