High frequency signal comparator for SHA-less analog-to-digital converters
US8773169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2010 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.