Interleaved digital to analog conversion
US8773296B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2012 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Sep 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3042
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for interleaving high-speed, delta-sigma based over-sampled DACs. A delta-sigma modulator is decomposed into a parallel poly-phase block-filter running at a lower rate. The generated parallel digital data is then fed directly to the analog DAC output stage where it is directly combined to form the full-rate signal using a 1-hot-of-N output stage. By using a poly-phase implementation, the complexity of the high-speed parallel digital-analog timing interface is simplified, along with the timing requirements of the delta-sigma modulator which normally would have to run at the full-oversampled rate. The 1-hot-of-N signal encoding is directly generated from the parallel delta-sigma modulator, and efficiently encodes the data in such a way to minimize signal-dependent supply noise. The architecture disclosed is advantageous for the practical implementation of high-speed over-sampled DACs, such as those used in stringent wireless applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.