Classifying traffic at a network node using multiple on-chip memory arrays
US8774177B2 · kind B2 · utility
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16References
15Claims
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Key dates
| Filing date | Jul 17, 2002 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Oct 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/61
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technique for classifying traffic at a network node includes programming multiple on-chip memory arrays with identical search entries, receiving multiple packets, and distributing classification searches related to the packets among the multiple on-chip memory arrays. In an embodiment, the on-chip memory arrays are content-addressable memory (CAM) arrays. In another embodiment, the distributing of classification searches related to the packets is performed in an alternating fashion with respect to a fixed order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.