Timing recovery method and apparatus for an input/output bus with link redundancy
US8774228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2011 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | May 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.