Method and apparatus to boost mass memory performance given power supply availability
US8775847B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2010 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Sep 23, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reliability of a power supply is assessed, such as for example considering one or more of the following: whether a host device is experiencing fast acceleration; whether a portable power supply has sufficient energy to meet current needs; whether a battery or removable memory cover is in place; and whether a software failure within the host device is imminent. In dependence on the assessed reliability, there is a selection made between a first mode and a second mode for operating a mass memory. The first mode comprises better data retention than the second mode for the case that the power supply is interrupted, and the second mode comprises faster data transfer than the first mode for the case that the power supply is not interrupted. In one embodiment the first and second mode buffers write data utilizing respective non-volatile (flash) and volatile (DRAM) memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.