IEEE1588 protocol negative testing method
US8775885B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Feb 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0667
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; obtaining the timing offset or path delay of the slave clock DUT before disturbance; assembling an abnormal message in a frame and sending it to the slave clock DUT; calculating the timing offset or path delay increment after disturbance of the abnormal message; determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, the test passes; otherwise the test fails. This testing method uses the field of correction field (correction Field) in the IEEE1588 message to “magnify” the response of the slave clock DUT to the abnormal message stimulus, and realizes a real-time closed-loop detection to efficiently verify whether the message processing logic of the slave clock DUT follows the IEEE1588 protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.