Thin film transistor array and displaying apparatus
US8779434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2008 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Nov 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/673
Abstract
A thin film transistor array is disclosed. The thin film transistor array includes plural gate electrodes formed on an insulation substrate, plural source electrodes formed above or under the gate electrodes via a gate insulation film so that the source electrodes cross the gate electrodes in a planar view, plural drain electrodes formed at corresponding positions surrounded by the gate electrodes and the source electrodes in a planar view in the same layer as that of the source electrodes, semiconductor layers formed via the gate insulation film to face the gate electrodes for forming corresponding channel regions between the source electrodes and the drain electrodes. The plural gate electrodes are linearly formed, and the channel regions are disposed to face the gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.