Field-effect transistor, semiconductor wafer, method for producing field-effect transistor and method for producing semiconductor wafer
US8779471B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 6, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Mar 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1≦1, 0≦y1≦1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0≦x2≦1, 0≦y2≦1, y2≠y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.