Spur suppression in a phase-locked loop
US8779817B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2013 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Dec 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1974
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digital circuits. Each clock dithering circuit is configured to dither flanks of a respective first and second clock input signal, and generate a dithered clock output signal, one for each of the sigma-delta modulator and digital circuits. A frequency of each dithered clock output signal follows a frequency of the respective first and second clock input signals, and a phase between each dithered clock output signal and the respective first and second clock input signal is shifted and constantly changing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.