Multi-phase voltage controlled oscillator using capacitance degenerated single ended transconductance stage and inductance/capacitance load
US8779861B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2011 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Dec 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electrical circuit includes a first transistor having a first source, a first drain, and a first gate, whereby the first transistor receives an input voltage through the first gate. An output voltage terminal outputs voltage from the first transistor and is connected to the first drain. A second transistor includes a second source, a second drain, and a second gate, whereby the second transistor receives a bias voltage through the second gate, and wherein the first source is connected to the second drain. A first capacitor is connected to the first source, the second source, and the second drain. An inductor is connected to the first drain. A second capacitor is connected in parallel with the inductor and further connected to the first drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.