Reduced memory vectored DSL
US8780686B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jul 22, 2011 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Jun 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/32
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The memory storage, transmission and processing demands of a vectored DSL system are reduced by sampling a subset of DSL tones in the DSL tone range used in the vectored system. This data is smoothed (denoised) to further reduce the data's size, sacrificing some fidelity or precision as a result. Finally, lossless entropy coding or the like is performed to encode the FEXT cancellation data for storage and use. The resulting data is less likely to cause transmission bottlenecks in the vectored system, can be stored and used more efficiently for both on-chip and off-chip vectoring implementations, and can be readily updated in various ways.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.