Method for emulating low frequency serial clock data recovery RF control bus operation using high frequency data
US8780962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | May 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W88/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system and method for emulating low frequency RF control bus operation using high frequency data is disclosed. In transmission path, the low frequency RFCB transmit data bytes are encoded and then up-sampled. The up-sampled data is then sent to hardware serializer for transmission. The resulting RF serial output stream appears to the external receiver to be encoded at low frequency even though the transceiver is operating at high frequency. In reception path, RFCB serial input data is de-serialized and then down-sampled. The down sampled data is then passed through custom byte-alignment logic and finally decoded. The transceivers are operated at high frequency but data is decoded and received as if it were at low rate. The FPGA serial transceiver are operated at a high frequency and sends each data bit a plurality of times to create a low effective data rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.