Channel phase estimation apparatus, demodulator, and receiving apparatus
US8780967B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Jan 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2647
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a channel phase estimation apparatus includes a phase memory, subtractor, multiplier, and adder. The phase memory is configured to store a first phase estimation value up to a (k−1)-th (for k=1, 2, . . . , K) symbol. The subtractor is configured to calculate a difference value between a phase value of one carrier of a k-th symbol and the first phase estimation value. The multiplier is configured to multiply the difference value by a weight. The adder is configured to add a value output from the multiplier and the first phase estimation value to output a second phase estimation value up to the k-th symbol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.