Symbol clock recovery circuit
US8781051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Jun 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2007/047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.