Memory area protection circuit
US8782367B2 · kind B2 · utility
1Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2007 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Dec 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.