Method and system for power-efficient and non-signal-degrading voltage regulation in memory subsystems
US8782452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2009 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Apr 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.