Dynamic and idle power reduction sequence using recombinant clock and power gating
US8782456B2 · kind B2 · utility
9Cited by
18References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2010 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Jan 4, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.