PRBS test memory interface considering DDR burst operation
US8782475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Mar 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56012
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The multiple cycles are transmitted through the interconnect to the external memory one after another such that a value of the data bit being transmitted is switched for each cycle. In another embodiment, an electronic component comprises an interface, a translation unit, and a test module. The translation module is configured to receive a burst from the external memory through the interface and is configured to translate the burst into a data word. The test module is configured to receive the data word from the translation module and is configured to compare the data word to a test pattern to detect an interconnect defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.